/*
 *---------------------------------------------------------------------------
 *
 *                  I N T E L   P R O P R I E T A R Y
 *
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT
 *     THE PRIOR WRITTEN PERMISSION OF :
 *
 *                        INTEL  CORPORATION
 *
 *                     2200 MISSION COLLEGE BLVD
 *
 *               SANTA  CLARA,  CALIFORNIA  95052-8119
 *
 *---------------------------------------------------------------------------
 */
#ifndef	__SYSTEM_INIT_C__
#define	__SYSTEM_INIT_C__

#include <dl_system.h>
#include <dl_buf.c>
#include <dl_meta.c>
#include <sig_functions.c>

void system_init()
{
	// Initialize the various scratch rings used in the ingress pipeline.

	InitScratchRing(POS_RX_TO_IPV4_SCR_RING_BASE, POS_RX_TO_IPV4_SCR_RING_SIZE, POS_RX_TO_IPV4_SCR_RING);
	InitScratchRing(IPV4_TO_QM_SCR_RING_BASE, IPV4_TO_QM_SCR_RING_SIZE, IPV4_TO_QM_SCR_RING);
	InitScratchRing(SCHEDULER_TO_QM_SCR_RING_BASE, SCHEDULER_TO_QM_SCR_RING_SIZE, SCHEDULER_TO_QM_SCR_RING);
	InitScratchRing(QM_TO_CSIX_TX_SCR_RING_BASE, QM_TO_CSIX_TX_SCR_RING_SIZE, QM_TO_CSIX_TX_SCR_RING);


	// Initialize the free buffer list
	Dl_BufInit();

	//	signal all MEs, except ME 0 (ME0 is running POS RX & this code)

	SignalMe(0x01, ME_INIT_SIGNAL);		// ME 1
	SignalMe(0x02, ME_INIT_SIGNAL);		// ME 2
	SignalMe(0x03, ME_INIT_SIGNAL);		// ME 3

	// The Next 4 MEs are in Cluster 1. 

	SignalMe(0x10, ME_INIT_SIGNAL);		// ME 4
	SignalMe(0x11, ME_INIT_SIGNAL);		// ME 5 is Queue Manager
										// ME 6 is CSIX Scheduler. Doesn't require this signal
	SignalMe(0x13, ME_INIT_SIGNAL);		// ME 7 CSIX TX

}


#endif		/* __ SYSTEM_INIT_C__ */