#                                                                      
#                  I N T E L   P R O P R I E T A R Y                   
#                                                                      
#     COPYRIGHT (c)  2001 BY  INTEL  CORPORATION.  ALL RIGHTS          
#     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
#     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
#     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
#     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
#     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
#     THE PRIOR WRITTEN PERMISSION OF :                                
#                                                                      
#                        INTEL  CORPORATION                            
#                                                                     
#                    2200 MISSION COLLEGE BLVD                        
#                                                                      
#               SANTA  CLARA,  CALIFORNIA  95052-8119 
#

#	convert \ to / in $IXA_SDK_DEV

ROOT= ${subst \,/, ${IXA_SDK_DEV}}

SRC_ROOT= ${ROOT}

DL_DIR= ${ROOT}/src/library/microblocks_library/microc
PDL_DIR= ./dispatch_loop
LIST_DIR= list
UOF_DIR=.

DL_LIB= ${DL_DIR}/dl_buf.c ${DL_DIR}/dl_meta.c ${DL_DIR}/sig_functions.c
PROJ_DL= ${PDL_DIR}/dl_source.c

RM= rm
MD= mkdir

DEFS_SIMULATION=	-DIXP_SIMULATION
DEFS_HARDWARE=		-DUSE_IMPORT_VAR

#	Default configuration is SIMULATION
#	Define in command line like make CONFIG=HARDWARE to change it

CONFIG?=	SIMULATION

DEFS=	${DEFS_${CONFIG}}

#	Note:	The -Qnew_schd is an Experimental optimisation flag for the compiler.
#	After successful completion of tests it will be available by default (i.e as 
#	part of -O2 flag)

CFLAGS= -Gx2400 -Qrevision_min=1 -O2 -Ob1 -W3 	\
		-Qbigendian -Qnctx=8 -Qnctx_mode=8 		\
		-Qnn_mode=0 -Qlm_start=0 -Zi 			\
		-Qnew_schd

GLOBAL_DEF= -DIXP2400 ${DEFS}

PACKET_RX_DIR= 	${SRC_ROOT}/src/building_blocks/rx/microengine/packet_rx/microc
IPV4_DIR= 		${SRC_ROOT}/src/building_blocks/ipv4/microc
PPP_DECAP_DIR=	${SRC_ROOT}/src/building_blocks/rx/microengine/l2_decap/ppp_decap/microc
CSIX_TX_DIR= 	${SRC_ROOT}/src/building_blocks/tx/microengine/csix_tx/microc
QM_DIR=			${SRC_ROOT}/src/building_blocks/queue_manager/qm_packet/microc
SCHEDULER_DIR=	${SRC_ROOT}/src/building_blocks/scheduler/scheduler_csix/microc



INCLUDE_DIR= 	-I${PDL_DIR}															\
				-I${DL_DIR}/../include													\
				-I${ROOT}/src/library/dataplane_library/microc							\
				-I${ROOT}/src/library/microblocks_library/microc						\
				-I${ROOT}/MicroEngineC/Include											\
				-I${ROOT}/src/include													\
				-I./																	\
				-I${PACKET_RX_DIR}														\
				-I${PPP_DECAP_DIR}														\
				-I${PPP_DECAP_DIR}/../include											\
				-I${IPV4_DIR}															\
				-I${IPV4_DIR}/../include												\
				-I${QM_DIR}																\
				-I${SCHEDULER_DIR}

#	
#	Dependcies. Manually specified.
#

PACKET_RX_FILES=	${PACKET_RX_DIR}/packet_rx.c 			\
					${PACKET_RX_DIR}/packet_rx_init.c 		\
					${PACKET_RX_DIR}/packet_rx_util.c 		\
					${PACKET_RX_DIR}/packet_rx.h 			\
					${DL_LIB} 								\
					${PROJ_DL}								\
					./system_init.c

IPV4_FILES= 		${PDL_DIR}/pos_ipv4.c					\
					${PPP_DECAP_DIR}/ppp.c					\
					${PPP_DECAP_DIR}/../include/ppp.h		\
					${DL_LIB} 								\
					${PROJ_DL}								\
					${IPV4_DIR}/ipv4_fwder.c				\
					${IPV4_DIR}/ipv4_fwder_util.c			\
					${IPV4_DIR}/ipv4_fwder_microc.h			\
					${IPV4_DIR}/../include/ipv4_fwder_uc.h

CSIX_TX_FILES=		${CSIX_TX_DIR}/csix_tx.c				\
					${CSIX_TX_DIR}/csix_tx_init.c			\
					${CSIX_TX_DIR}/csix_tx_util.c			\
					${CSIX_TX_DIR}/csix_tx_c.h

QM_FILES=			${QM_DIR}/qm_packet.c					\
					${QM_DIR}/qm_internal.c					\
					${QM_DIR}/qm_packet.h

SCHEDULER_FILES=	${SCHEDULER_DIR}/scheduler.c			\
					${SCHEDULER_DIR}/scheduler_flow_control.c		\
					${SCHEDULER_DIR}/scheduler_qm.c			\
					${SCHEDULER_DIR}/scheduler.h


LIST_FILES= 		${LIST_DIR}/packet_rx.list					\
					${LIST_DIR}/pos_ipv4_a.list					\
					${LIST_DIR}/pos_ipv4_b.list					\
					${LIST_DIR}/pos_ipv4_c.list					\
					${LIST_DIR}/pos_ipv4_d.list					\
					${LIST_DIR}/qm.list							\
					${LIST_DIR}/scheduler.list					\
					${LIST_DIR}/csix_tx.list

MC_LIB= 			${ROOT}/MicroengineC/src/intrinsic.c 				\
					${ROOT}/MicroengineC/src/libc.c						\
					${ROOT}/MicroengineC/src/rtl.c 						\
					${ROOT}/MicroengineC/samples/util/util.c


default:: ${UOF_DIR}/oc48_pos_ingress.uof


${UOF_DIR}/oc48_pos_ingress.uof: ${LIST_FILES}
	ucld 	-u 0 	${LIST_DIR}/packet_rx.list				\
			-u 1 	${LIST_DIR}/pos_ipv4_a.list				\
			-u 2 	${LIST_DIR}/pos_ipv4_b.list				\
			-u 3	${LIST_DIR}/qm.list						\
			-u 16	${LIST_DIR}/scheduler.list				\
			-u 17 	${LIST_DIR}/pos_ipv4_c.list				\
			-u 18	${LIST_DIR}/pos_ipv4_d.list				\
			-u 19	${LIST_DIR}/csix_tx.list				\
			-g 												\
			-sc 	0x00000000:0x00000000 					\
			-dr 	0x00000010:0x00000000 					\
			-sr0 	0x01100000:0x00008000 					\
			-sr1 	0x00000004:0x00000000 					\
			-sr2 	0x00000004:0x00000000 					\
			-sr3 	0x00000004:0x00000000 					\
			-o 		${UOF_DIR}/oc48_pos_ingress.uof

#
#	packet_rx doesn't work with -Qnew_opt flag. We can ovrecome that by 
#	using -mP3OPT_ixp_spare9=0. This is all experimental. Not meant for 
#	general users.
#

${LIST_DIR}/packet_rx.list: ${PACKET_RX_FILES}

	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF}				\
		-Qnn_mode=0											\
		-DPPP_RECEIVE										\
		-D_DEBUG_											\
		-DPPP_2_BYTE_HEADER									\
		-DMETA_CACHE_SIZE=8									\
		-DBIGENDIAN											\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/packet_rx.list						\
		 ${MC_LIB}											\
		 ${PACKET_RX_DIR}/packet_rx.c						\
		 ./system_init.c

${LIST_DIR}/pos_ipv4_a.list: ${IPV4_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR}	${GLOBAL_DEF}			\
		-Qnn_mode=1											\
		-Qnew_schd											\
		-Qspill=1											\
		-DMICROENGINE 										\
		-DCHIP_VERSION=IXP2XXX 								\
		-DRFC1812_SHOULD 									\
		-DMETA_CACHE_SIZE=8 								\
		-DIPV4_START_ME 									\
		-DDL_NEXT_ME=0x02 									\
		-DIP_HDR_OFFSET=2 									\
		-DRFC2644_CHECKS 									\
		-DNEXTHOP_INFO_SRAM 								\
		-DDBCAST_TABLE_BLOCK_SIZE=8 						\
		-DPROCESS_CONTROL_BLOCK								\
		-DPPP_RECEIVE 										\
		-DPPP_2_BYTE_HEADER									\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/pos_ipv4_a.list						\
		 ${MC_LIB}											\
		 ${PDL_DIR}/pos_ipv4.c

${LIST_DIR}/pos_ipv4_b.list: ${IPV4_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF}				\
		-Qnn_mode=1											\
		-Qnew_schd											\
		-Qspill=1											\
		-DMICROENGINE 										\
		-DCHIP_VERSION=IXP2XXX 								\
		-DRFC1812_SHOULD 									\
		-DMETA_CACHE_SIZE=8 								\
		-DDL_NEXT_ME=0x11 									\
		-DIP_HDR_OFFSET=2 									\
		-DRFC2644_CHECKS 									\
		-DNEXTHOP_INFO_SRAM 								\
		-DDBCAST_TABLE_BLOCK_SIZE=8 						\
		-DPROCESS_CONTROL_BLOCK 							\
		-DPPP_RECEIVE 										\
		-DPPP_2_BYTE_HEADER									\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/pos_ipv4_b.list						\
		 ${MC_LIB}											\
		 ${PDL_DIR}/pos_ipv4.c



${LIST_DIR}/pos_ipv4_c.list: ${IPV4_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF}				\
		-Qnn_mode=1											\
		-Qnew_schd											\
		-Qspill=1											\
		-DMICROENGINE 										\
		-DCHIP_VERSION=IXP2XXX 								\
		-DRFC1812_SHOULD 									\
		-DMETA_CACHE_SIZE=8 								\
		-DDL_NEXT_ME=0x12 									\
		-DIP_HDR_OFFSET=2 									\
		-DRFC2644_CHECKS 									\
		-DNEXTHOP_INFO_SRAM 								\
		-DDBCAST_TABLE_BLOCK_SIZE=8 						\
		-DPROCESS_CONTROL_BLOCK 							\
		-DPPP_RECEIVE 										\
		-DPPP_2_BYTE_HEADER									\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/pos_ipv4_c.list						\
		 ${MC_LIB}											\
		 ${PDL_DIR}/pos_ipv4.c

${LIST_DIR}/pos_ipv4_d.list: ${IPV4_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF} 			\
		-Qnn_mode=1											\
		-Qnew_schd											\
		-Qspill=1											\
		-DMICROENGINE 										\
		-DCHIP_VERSION=IXP2XXX 								\
		-DRFC1812_SHOULD 									\
		-DMETA_CACHE_SIZE=8 								\
		-DDL_NEXT_ME=0x1 									\
		-DIP_HDR_OFFSET=2 									\
		-DRFC2644_CHECKS 									\
		-DNEXTHOP_INFO_SRAM 								\
		-DDBCAST_TABLE_BLOCK_SIZE=8 						\
		-DPROCESS_CONTROL_BLOCK 							\
		-DPPP_RECEIVE 										\
		-DPPP_2_BYTE_HEADER									\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/pos_ipv4_d.list						\
		 ${MC_LIB}											\
		 ${PDL_DIR}/pos_ipv4.c

${LIST_DIR}/csix_tx.list : ${CSIX_TX_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF}				\
		-Qnn_mode=0											\
		-Qnew_schd											\
		-DDL_META_DATA_IN_READ_SXFER						\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/csix_tx.list							\
		 ${MC_LIB}											\
		 ${CSIX_TX_DIR}/csix_tx.c							\
		 ${CSIX_TX_DIR}/csix_tx_init.c


${LIST_DIR}/qm.list	:		${QM_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF}				\
		-Qnn_mode=0											\
		-Qnew_schd											\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/qm.list								\
		 ${MC_LIB}											\
		 ${QM_DIR}/qm_packet.c	


${LIST_DIR}/scheduler.list	:	${SCHEDULER_FILES}

	uccl ${CFLAGS} ${INCLUDE_DIR} ${GLOBAL_DEF}				\
		-Qnn_mode=0											\
		-Qnew_schd											\
 		-Fo${LIST_DIR}/										\
		-Fe${LIST_DIR}/scheduler.list						\
		 ${MC_LIB}											\
		 ${SCHEDULER_DIR}/scheduler.c						\
		 ${SCHEDULER_DIR}/scheduler_flow_control.c			\
		 ${SCHEDULER_DIR}/scheduler_qm.c

clean::
	-${RM}	${LIST_DIR}/*.list ${LIST_DIR}/*.uci ${LIST_DIR}/*.ucp ${UOF_DIR}/*.uof 2>/dev/null	
	-${RM}  ${LIST_DIR}/*.obj  ${LIST_DIR}/*.dbg ${LIST_DIR}/*.hex 2>/dev/null
	-${RM}  ./*.hex 2>/dev/null
