Selected Journal Publications

  • G. Li, D. Kagaris, "On the Number of Maintenance Cycles in Systems with Critical and Non-Critical Components,'' IEEE Transactions on Reliability, v. 73. n. 2, pp. 1044-1059, June 2024.
  • G. Li, D. Kagaris, "Time-Domain Computation of the Reliability of Standby Systems With and Without Priority Under General Repair,'' Computers & Industrial Engineering (Elsevier), March 2024.
  • S. Kundan, T. Marinakis, I. Anagnostopoulos, D. Kagaris, "A Pressure-Aware Policy for Contention Minimization on Multi-Core Systems,'' ACM Transactions on Architecture and Code Optimization, 19(3): 40:1-40:26, 2022.
  • D. Kagaris, S. Dutta, S. Eyerman, "Execution Time Estimation of Multithreaded Programs With Critical Sections,'' IEEE Transactions on Parallel and Distributed Systems, v. 33, n. 10, pp. 2470-2481, Oct. 2022.
  • J. Suda, D. Kagaris, "Automated Diagnosis of Engine Misfire Faults Using Combination Classifiers,'' SAE International Journal of Commercial Vehicles, v. 13, n. 2, pp. 103--113, 2020.
  • D. Kagaris, S. Dutta, "Scheduling Mutual Exclusion Accesses in Equal-Length Jobs,'' ACM Transactions on Parallel Computing, vol. 6, no. 2, Article 8, 26 pages, Aug. 2019.
  • A. Khamesipour, D. Kagaris, "Speeding up the Discovery of Combinations of Differentially Expressed Genes for Disease Prediction and Classification,'' Computer Methods and Programs in Biomedicine, 170:69-80, Mar. 2019.
  • D. Kagaris, A. Khamesipour, C. T. Yiannoutsos, "AUCTSP: An Improved Biomarker Gene Pair Class Predictor,'' BMC Bioinformatics, v. 19, pp. 244-256, Jun. 2018.
  • O. Acevedo, D. Kagaris, "On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation," IEEE Transactions on Computers, v. 65, n. 2, pp. 664-669, Feb. 2016.
  • D. Kagaris, "MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 35, n. 1, pp. 114-127, Jan. 2016.
  • D. Kagaris, C. T. Yiannoutsos, "A Multi-Index ROC-Based Methodology for High Throughput Experiments in Gene Discovery,'' International Journal of Data Mining and Bioinformatics (InderScience) , v. 8, n. 1, pp. 42-65, 2013.
  • D. Kagaris, "Maximizing the Lifetime of a Wireless Sensor Network with Fixed Targets,'' Ad Hoc and Sensor Wireless Networks, v. 17, n. 3-4,  pp. 253 - 268, 2013.
  • D. Nikolos, D. Kagaris, S. Sudireddy, S. Gidaros, "An Improved Search Method for Accumulator-Based Test Set Embedding,'' IEEE Transactions on Computers, v. 58, n. 1, pp. 132-138, Jan. 2009.
  • J. Kakade, D. Kagaris, D.K. Pradhan, "Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 27, n. 9, pp. 1689-1692, Sept. 2008.
  • J. Kakade, D. Kagaris, "Minimization of Linear Dependencies through the Use of Phase Shifters,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 26, n. 10, pp. 1877-1882, Oct. 2007.
  • D. Kagaris, T. Haniotakis, "A Methodology for Transistor-Efficient Supergate Design," IEEE Transactions on VLSI Systems, v. 15, n. 4, pp. 488-492, Apr. 2007.
  • D. Kagaris, "Improved TDM Switching Assignments for Variable and Fixed Burst Length," International Journal of Satellite Communications and Networking, v. 25, pp. 93-107, 2007.
  • D. Kagaris, P. Karpodinis, D. Nikolos, "A Method for Accumulator-Based Test-per-Scan BIST," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v. 25, n. 11, pp. 2578-2586, Nov. 2006.
  • D. Kagaris, "A Similarity Transform for Linear Finite State Machines," Discrete Applied Mathematics, vol. 154, pp. 1570-1577, 2006.
  • D. Kagaris, R. Aakuthota, A. Verma, "Maximum Sequence Test Pattern Generators with Irreducible Characteristic Polynomials," Microprocessors and Microsystems, v. 30, n. 2, pp. 117-123, Mar. 2006.
  • D. Kagaris, S. Tragoudas, S. Kuriakose, "InTeRail: A Test Architecture for Core-Based SOCs," IEEE Transactions on Computers, v. 55, n. 2, pp. 137-149, Feb. 2006.
  • D. Mehta, D. Kagaris, R. Viswanathan, "Throughput Performance of an Adaptive ARQ Scheme in Rayleigh Fading Channels," IEEE Transactions on Wireless Communications, v. 5, n. 1, pp. 12-15, Jan. 2006.
  • D. Kagaris, "Phase Shifter Merging," Journal of Electronic Testing: Theory and Applications, vol. 21, no. 2, pp. 161-168, April 2005.
  • D. Kagaris, "A Unified Method for Phase Shifter Computation," ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 1, pp. 157-167, Jan. 2005.
  • D. Kagaris, "Multiple-Seed TPG Structures," IEEE Transactions on Computers, vol. 52, no. 12, pp. 1633-1639, Dec. 2003.
  • D. Kagaris, "On Minimum Delay Clustering Without Replication," Integration, the VLSI Journal, vol. 36, no.1, pp. 27-39, Sep. 2003.
  • D. Kagaris, S. Tragoudas, "LFSR Characteristic Polynomials for Pseudoexhaustive TPG with Low Number of Seeds," Journal of Electronic Testing: Theory and Applications, vol. 19, no. 3, pp. 233--244, June 2003.
  • D. Kagaris, S. Tragoudas, "On the Non-Emumerative Path Fault Simulation Problem," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp.1095-1100, Sep. 2002.
  • D. Kagaris, "Linear Dependencies in Extended LFSMs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, pp. 852-858, July 2002.
  • D. Kagaris, S. Tragoudas, "Using a WLFSR to Embed Test Pattern Pairs in Minimum Time," Journal of Electrical Testing: Theory and Applications, vol. 18, no. 3, pp. 305-313, June 2002.
  • D. Kagaris, S. Tragoudas, "Von Neumann Hybrid Cellular Automata for Generating Deterministic Test Sequences," ACM Transactions on Design Automation of Electronic Systems, vol. 6, no. 3, pp. 308-321, 2001.
  • D. Kagaris, S. Tragoudas, "Computational Analysis of Counter-Based Schemes for VLSI Test Pattern Generation," Discrete Applied Mathematics, vol. 110, pp. 227-250, 2001.
  • D. Kagaris, S. Tragoudas, A. Majumdar, "Test-Set Partitioning for Multi-Weighted Random LFSRs," Integration, the VLSI Journal, vol. 30, pp. 65-75, 2000.
  • D. Kagaris, S. Tragoudas, "On the Design of Optimal Counter-Based Schemes for Test Set Embedding," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 219-230, 1999.
  • D. Kagaris, S. Tragoudas, "Maximum Weighted Independent Sets on Transitive Graphs and Applications," Integration, the VLSI Journal, vol. 27, pp. 77-86, 1999.
  • D. Kagaris, G. E. Pantziou, S. Tragoudas, C. D. Zaroliagis, "On the Computation of Fast Data Transmissions in Networks with Capacities and Delays," Networks, 33:(3), 167-174, 1999.
  • D. Kagaris, "A Routing Algorithm for Row-Based FPGAs" Microprocessors and Microsystems, vol. 20, no. 7, pp. 401-407, 1997.
  • D. Kagaris, S. Tragoudas, D. Karayiannis, "Improved Nonenumerative Path Delay Fault Coverage Estimation based on Optimal Polynomial-Time Algorithms," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 3, pp. 309-315, 1997.
  • D. Kagaris, S. Tragoudas, A. Majumdar, "On the Use of Counters for Deterministic Test Pattern Generation," IEEE Transactions on Computers, vol. 45, no. 12, pp. 1405-1419, 1996.
  • D. Kagaris, S. Tragoudas, "A Fast Algorithm for Minimizing FPGA Combinational and Sequential Modules," ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 3, pp. 341-351, 1996.
  • D. Kagaris, S. Tragoudas, "Retiming--Based Partial Scan," IEEE Transactions on Computers, vol. 45, no. 1, pp. 74-87, 1996.
  • D. Kagaris, S. Tragoudas, D. Bhatia, "Pseudo-Exhaustive Built-In TPG for Sequential Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no 9, pp.1160-1171, 1995.
  • D. Kagaris, S. Tragoudas, "Avoiding Linear Dependencies in LFSR Test Pattern Generators," Journal of Electronic Testing: Theory and Applications, vol. 6, pp. 229-241, 1995.
  • D. Kagaris, F. Makedon, S. Tragoudas, "A Method for Pseudo-Exhaustive Test Pattern Generation,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 9, pp. 1170-1178, 1994.
  • D. Kagaris, S. Tragoudas, "Cost-Effective LFSR Synthesis for Optimal Pseudo-Exhaustive BIST Test Sets," IEEE Transactions on VLSI Systems, vol. 4, no. 1, pp. 526-536, 1993.